Posted: January 31st, 2023

(Sections 2.2 and 2.3) Here is the skeleton of part of a program that simulatesthe memory hierarchy of a computer system

(Sections 2.2 and 2.3) Here is the skeleton of part of a program that simulatesthe memory hierarchy of a computer system. Only the instruction fetch simulationis outlined:Get_next_tuple (operation,vaddress);case: operation = 0/* we have an instruction fetch*/Extract_TLB_fields;Check_TLB;If not TLBhit then Get_PTE_from_Main_Memory;Get_physical_address;Extract_cache_fields;Check_cache;If not cachehit then Get_Cache_Block_from_Main_Memory;Put instruction in IR;case: . . ..From the instruction fetch viewpoint, the hierarchy consists of a four-way setassociativeTLB of 64 entries and a two-way 8 KB set-associative cache with 32byte lines (each instruction is 4 bytes). Both structures use an LRU replacementalgorithm.The computer system runs under an operating system with paging. The pagesize is 4 KB. Both virtual and physical addresses are 32 bits.The input to the program is a trace of tuples (operation,addresses). An operationof value 0 indicates an instruction fetch.(a) The routine “Extract TLB fields” takes a 32-bit address, called vaddress, asinput parameter. It should return two values: tagtlb and indextlb, which willbe used to check the TLB. Indicate in pseudocode how you would get them.An example of pseudocode (with no particular meaning) is:xyz = abc shifted right by 16;xyz = xyz and 0x0000 00ff(b) The routine “Check TLB” takes tagtlb and indextlb as input parameters. Itreturns a Boolean value TLBhit indicating whether there is a TLB hit ora TLB miss. In the case of a hit, it returns also a physical frame numbervalue that indicates the mapping between the virtual page number andthe physical frame number. (You can assume that on a TLB hit there isno page fault.) In the worst case, how many comparisons are needed in“Check TLB” to see whether you have a hit or a miss? What are the theoreticalminimum and maximum values of physical frame number? If thefirst 16 K of physical memory are reserved for the operating system and I/Oand are not pageable, and if the physical memory is 256 MB, what are thereal minimum and maximum values of physical frame number?Exercises 12–15 73(c) In the case of a miss, the routine “Get PTE from Main Memory” willreturn physical frame number. The routine “Get physical address” takesvaddress and physical frame number as input parameters and returns a32-bit physical address value. Write the pseudocode for “Get physicaladdress”.(d) The routine “Extract cache fields” takes physical address as input parameterand returns two values: tagcache and indexcache, which will be used toaccess the cache. Write the pseudocode for this routine.(e) Assume: No page fault. It takes 1 cycle to obtain physical address in the case of a TLB hit, and100 cycles in the case of a TLB miss. Once physical address has been obtained, it takes 1 cycle to get theinstruction in IF/ID in the case of a cache hit, and 50 cycles in the caseof a cache miss.If the TLB hit rate is 0.995 and the cache hit rate is 0.97, what is the average instructionfetch time?