Question Assignment description
Design a finite state machine(FSM)that cycles by the final 4digits of your UTEP scholar ID in a loop. In your design there ought to be an enter that adjustments thedirection of the cycle.Every variety of the ID ought to be displayed on the seven-segment display whereas the present state of the FSM ought to be displayed on its corresponding LED.Non-valid states ought to preserve all LEDs off.implement a clock because the synchronizing clock sign.For Instance,a selected scholar has the ID 80-210543. The state diagram and outputs for his design are as followsFor Instance, a selected scholar has ID 80210543. The state diagram and outputs for his de signal are as follows:zero @state05 @state14 @state23 @state3and then display backwardsPre-LabDraft the behavioral Verilog module for the FSM.Trace: You might use anif/ifelse/else assertion or a“nested”case assertion.Trace: search “Finite State Machines” inIntroduction to Verilog-P.M.Nyasulu
